In display panels, a gate driving signal is generally provided to the gate of an individual thin film transistor (TFT) of a pixel area via a gate driving circuit. The gate driving circuit may be integrated on an array substrate of a display panel by an array process, i.e., the gate driver on array (GOA) process. Such an integration process not only saves cost, but may also achieve an aesthetic design in which both sides of the display panel are symmetric, and meanwhile, also omits the binding area for the gate driving circuit and the fan-out wiring space, which may thus implement a narrow border design, moreover, such an integration process may further omit the binding process in the direction of gate scanning lines, and thereby improves the productivity and yield.
Nowadays, in shift register units at each stage in an existing gate driving circuit, the current of the control clock signal CLK loaded to a TFT of the signal output terminal Output is relatively large, the size of the TFT is relatively large, and the parasitic capacitance of the TFT is relatively large. When the potential of the clock signal CLK inputted at the source of the TFT changes from low level to high level, since the TFT has a relatively large parasitic capacitance, the potential of the gate of the TFT will be caused to rise too, which will thus cause the TFT to be erroneously turned on, and as such, the clock signal CLK inputted at the source of the TFT will be erroneously provided to the signal output terminal Output which is coupled to the drain of the TFT, and then poor display such as picture abnormality, black screen, etc. will be caused to occur to the display panel.
Therefore, how to avoid the TFT error turn-on that the control clock signal is loaded to the signal output terminal is a technical problem that urgently needs to be solved by the skilled in the art.